; ------------------------------------------------------------------------
;      MODS320
;      REV.  1.0    JUNE 23, 1993 for DS80C320
P0     DATA  080H  ;PORT 0
SP     DATA  081H  ;STACK POINTER
DPL    DATA  082H  ;DATA POINTER 0 - LOW BYTE
DPH    DATA  083H  ;DATA POINTER 0 - HIGH BYTE
DPL1   DATA  084H  ;DATA POINTER 1 - LOW BYTE
DPH1   DATA  085H  ;DATA POINTER 1 - HIGH BYTE
DPS    DATA  086H  ;DATA POINTER SELECT
PCON   DATA  087H  ;POWER CONTROL
TCON   DATA  088H  ;TIMER CONTROL
TMOD   DATA  089H  ;TIMER MODE
TL0    DATA  08AH  ;TIMER 0 - LOW BYTE
TL1    DATA  08BH  ;TIMER 1 - LOW BYTE
TH0    DATA  08CH  ;TIMER 0 - HIGH BYTE
TH1    DATA  08DH  ;TIMER 1 - HIGH BYTE
CKCON  DATA  08EH  ;CLOCK CONTROL
P1     DATA  090H  ;PORT 1
EXIF   DATA  091H  ;EXTERNAL INTERRUPT FLAG
SCON   DATA  098H  ;SERIAL PORT CONTROL
SBUF   DATA  099H  ;SERIAL PORT BUFFER
P2     DATA  0A0H  ;PORT 2
IE     DATA  0A8H  ;INTERRUPT ENABLE
SADDR0 DATA  0A9H  ;SLAVE ADDRESS ZERO
SADDR1 DATA  0AAH  ;SLAVE ADDRESS ONE
P3     DATA  0B0H  ;PORT 3
IP     DATA  0B8H  ;INTERRUPT PRIORITY
SADEN0 DATA  0B9H  ;SLAVE ADDRESS MASK ENABLE ZERO
SADEN1 DATA  0BAH  ;SLAVE ADDRESS MASK ENABLE ONE
SCON1  DATA  0C0H  ;SERIAL PORT ONTROL ONE
SBUF1  DATA  0C1H  ;SERIAL DATA BUFFER ONE
TA     DATA  0C7H  ;TIMED ACCESS
T2CON  DATA  0C8H  ;TIMER TWO CONTROL
T2MOD  DATA  0C9H  ;TIMER TWO MODE CONTROL
RCAP2L DATA  0CAH  ;LEAST SIGNIFICANT BYTE CAPTURE OF TIMER 2
RCAP2H DATA  0CBH  ;MOST SIGNIFICANT BYTE CAPTURE OF TIMER 2
TL2    DATA  0CCH  ;TIMER 2 LSB
TH2    DATA  0CDH  ;TIMER 2 MSB
PSW    DATA  0D0H  ;PROGRAM STATUS WORD
WDCON  DATA  0D8H  ;WATCHDOG CONTROL
ACC    DATA  0E0H  ;ACCUMULATOR
EIE    DATA  0E8H  ;EXTENDED INTERRUPT ENABLE
B      DATA  0F0H  ;MULTIPLICATION REGISTER
EIP    DATA  0F8H  ;EXTENDED INTERRUPT PRIORITY
IT0    BIT   088H  ;TCON.0 - EXT. INTERRUPT 0 TYPE
IE0    BIT   089H  ;TCON.1 - EXT. INTERRUPT 0 EDGE FLAG
IT1    BIT   08AH  ;TCON.2 - EXT. INTERRUPT 1 TYPE
IE1    BIT   08BH  ;TCON.3 - EXT. INTERRUPT 1 EDGE FLAG
TR0    BIT   08CH  ;TCON.4 - TIMER 0 ON/OFF CONTROL
TF0    BIT   08DH  ;TCON.5 - TIMER 0 OVERFLOW FLAG
TR1    BIT   08EH  ;TCON.6 - TIMER 1 ON/OFF CONTROL
TF1    BIT   08FH  ;TCON.7 - TIMER 1 OVERFLOW FLAG
T2     BIT   090H  ;
T2EX   BIT   091H  ;
RXD1   BIT   092H  ;
TXD1   BIT   093H  ;
INT2   BIT   094H  ;
INT3   BIT   095H  ;
INT4   BIT   096H  ;
INT5   BIT   097H  ;
RI_0   BIT   098H  ;SCON.0 - RECEIVE INTERRUPT FLAG
TI_0   BIT   099H  ;SCON.1 - TRANSMIT INTERRUPT FLAG
RB8_0  BIT   09AH  ;SCON.2 - RECEIVE BIT 8
TB8_0  BIT   09BH  ;SCON.3 - TRANSMIT BIT 8
REN_0  BIT   09CH  ;SCON.4 - RECEIVE ENABLE
SM2_0  BIT   09DH  ;SCON.5 - SERIAL MODE CONTROL BIT 2
SM1_0  BIT   09EH  ;SCON.6 - SERIAL MODE CONTROL BIT 1
SM0    BIT   09FH  ;SCON.7 - SERIAL MODE CONTROL BIT 0
FE_0   BIT   09FH  ;SCON.7 - FRAMING ERROR FLAG
EX0    BIT   0A8H  ;IE.0 - EXTERNAL INTERRUPT 0 ENABLE
ET0    BIT   0A9H  ;IE.1 - TIMER 0 INTERRUPT ENABLE
EX1    BIT   0AAH  ;IE.2 - EXTERNAL INTERRUPT 1 ENABLE
ET1    BIT   0ABH  ;IE.3 - TIMER 1 INTERRUPT ENABLE
ES0    BIT   0ACH  ;IE.4 - SERIAL PORT 0 INTERRUPT ENABLE
ET2    BIT   0ADH  ;IE.5 - TIMER 2 INTERRUPT ENABLE
ES1    BIT   0AEH  ;IE.6 - SERIAL PORT 1 INTERRUPT ENABLE
EA     BIT   0AFH  ;IE.7 - GLOBAL INTERRUPT ENABLE
RXD0   BIT   0B0H  ;P3.0 - SERIAL PORT RECEIVE INPUT
TXD0   BIT   0B1H  ;P3.1 - SERIAL PORT TRANSMIT OUTPUT
INT0   BIT   0B2H  ;P3.2 - EXTERNAL INTERRUPT 0 INPUT
INT1   BIT   0B3H  ;P3.3 - EXTERNAL INTERRUPT 1 INPUT
T0     BIT   0B4H  ;P3.4 - TIMER 0 COUNT INPUT
T1     BIT   0B5H  ;P3.5 - TIMER 1 COUNT INPUT
WR     BIT   0B6H  ;P3.6 - WRITE CONTROL FOR EXT. MEMORY
RD     BIT   0B7H  ;P3.7 - READ CONTROL FOR EXT. MEMORY
PX0    BIT   0B8H  ;IP.0 - EXTERNAL INTERRUPT 0 PRIORITY
PT0    BIT   0B9H  ;IP.1 - TIMER 0 PRIORITY
PX1    BIT   0BAH  ;IP.2 - EXTERNAL INTERRUPT 1 PRIORITY
PT1    BIT   0BBH  ;IP.3 - TIMER 1 PRIORITY
PS0    BIT   0BCH  ;IP.4 - SERIAL PORT PRIORITY
PT2    BIT   0BDH
PS1    BIT   0BEH
RI_1   BIT   0C0H  ;SCON1.0 - RECEIVE INTERRUPT FLAG
TI_1   BIT   0C1H  ;SCON1.1 - TRANSMIT INTERRUPT FLAG
RB8_1  BIT   0C2H  ;SCON1.2 - RECEIVE BIT 8
TB8_1  BIT   0C3H  ;SCON1.3 - TRANSMIT BIT 8
REN_1  BIT   0C4H  ;SCON1.4 - RECEIVE ENABLE
SM2_1  BIT   0C5H  ;SCON1.5 - SERIAL MODE CONTROL BIT 2
SM1_1  BIT   0C6H  ;SCON1.6 - SERIAL MODE CONTROL BIT 1
SM0_1  BIT   0C7H  ;SCON1.7 - SERIAL MODE CONTROL BIT 0
FE_1   BIT   0C7H  ;
CP_RL2 BIT   0C8H  ;T2CON.0 - TIMER 2 CAPTURE/COMPARE
C_T2   BIT   0C9H  ;T2CON.1 - TIMER 2 COUNT/RELOAD
TR2    BIT   0CAH  ;T2CON.2 - TIMER 2 RUN ENABLE
EXEN2  BIT   0CBH  ;T2CON.3 - TIMER 2 EXTERNAL ENABLE
TCLK   BIT   0CCH  ;T2CON.4 - SERIAL TRANSMIT CLOCK
RCLK   BIT   0CDH  ;T2CON.5 - SERIAL RECIEVE CLOCK
EXF2   BIT   0CEH  ;T2CON.6 - TIMER 2 EXTERNAL FLAG
TF2    BIT   0CFH  ;T2CON.7 - TIMER 2 OVERFLOW FLAG
P      BIT   0D0H  ;PSW.0 - ACCUMULATOR PARITY FLAG
F1     BIT   0D1H  ;PSW.1 - FLAG 1
OV     BIT   0D2H  ;PSW.2 - OVERFLOW FLAG
RS0    BIT   0D3H  ;PSW.3 - REGISTER BANK SELECT 0
RS1    BIT   0D4H  ;PSW.4 - REGISTER BANK SELECT 1
F0     BIT   0D5H  ;PSW.5 - FLAG 0
AC     BIT   0D6H  ;PSW.6 - AUXILIARY CARRY FLAG
CY     BIT   0D7H  ;PSW.7 - CARRY FLAG
RWT    BIT   0D8H  ;WDCON.0 - RESET WATCHDOG TIMER
EWT    BIT   0D9H  ;WDCON.1 - ENABLE WATCHDOG TIMER RESET
WTRF   BIT   0DAH  ;WDCON.2 - WATCHDOG TIMER RESET FLAG
WDIF   BIT   0DBH  ;WDCON.3 - WATCHDOG INTERRUPT FLAG
PFI    BIT   0DCH  ;WDCON.4 - POWER FAIL INTERRUPT FLAG
EPFI   BIT   0DDH  ;WDCON.5 - ENABLE POWER FAIL INTERRUPT
POR    BIT   0DEH  ;WDCON.6 - POWER-ON RESET FLAG
SMOD   BIT   0DFH  ;WDCON.7 - SERIAL MODIFICATION 1
EX2    BIT   0E8H  ;EIE.0 - ENABLE EXTERNAL INTERRUPT 2
EX3    BIT   0E9H  ;EIE.1 - ENABLE EXTERNAL INTERRUPT 3
EX4    BIT   0EAH  ;EIE.2 - ENABLE EXTERNAL INTERRUPT 4
EX5    BIT   0EBH  ;EIE.3 - ENABLE EXTERNAL INTERRUPT 5
EWDI   BIT   0ECH  ;EIE.4 - ENABLE WATCHDOG INTERRUPT
PX2    BIT   0F8H  ;EIP.0 - EXTERNAL INTERRUPT 2 PRIORITY
PX3    BIT   0F9H  ;EIP.1 - EXTERNAL INTERRUPT 3 PRIORITY
PX4    BIT   0FAH  ;EIP.2 - EXTERNAL INTERRUPT 4 PRIORITY
PX5    BIT   0FBH  ;EIP.3 - EXTERNAL INTERRUPT 5 PRIORITY
PWDI   BIT   0FCH  ;EIP.4 - WATCHDOG INTERRUPT PRIORITY

