Ahoj, som si upravil makefile nech pracuje len zo súbormi ktoré ma v projekte a teraz ak si vytvorím noví project alebo si ho prenesiem na iný pc tak ho len nakopírujem a pôjde skompilovať pretože sa neodkazuje na žiadne súbory mimo a tak tiež som pridal nech zobrazuje veľkosť použitých dát v mcu.
Kód: Vybrat vše
#-----------------------------------------------------------------------------
#
# W7500 compilation make file
#
#-----------------------------------------------------------------------------
#
# Configurations
#
# Choose the core instantiated, can be
# - CORTEX_M0
# - CORTEX_M0PLUS
#CPU_PRODUCT = CORTEX_M0PLUS
CPU_PRODUCT = CORTEX_M0
TOOL_CHAIN = gcc
CPU_TYPE = -mcpu=cortex-m0
GNU_CC = arm-none-eabi-gcc
GNU_OBJDUMP = arm-none-eabi-objdump
GNU_OBJCOPY = arm-none-eabi-objcopy
GNU_SIZE = arm-none-eabi-size
GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
TESTNAME = main
# ---------------------------------------------------------------------------------------
all: all_$(TOOL_CHAIN)
# ---------------------------------------------------------------------------------------
# ---------------------------------------------------------------------------------------
# gcc :
all_gcc:
$(GNU_CC) $(GNU_CC_FLAGS)\
startup_W7500.S \
*.c \
$(USER_DEFINE) -T gcc_W7500.ld -o obj\Debug\$(TESTNAME).o \
# Generate disassembly code
$(GNU_OBJDUMP) -S obj\Debug\$(TESTNAME).o > obj\Debug\$(TESTNAME).lst
# Generate binary file
$(GNU_OBJCOPY) -S obj\Debug\$(TESTNAME).o -O binary bin\Debug\$(TESTNAME).bin
# Generate hex file
$(GNU_OBJCOPY) -S obj\Debug\$(TESTNAME).o -O verilog bin\Debug\$(TESTNAME).hex
arm-none-eabi-size obj\Debug\$(TESTNAME).o
# ---------------------------------------------------------------------------------------
# Clean
clean :
@rm -rf *.o
@if [ -e bin\Debug\$(TESTNAME).hex ] ; then \
rm -rf bin\Debug\$(TESTNAME).hex ; \
fi
@if [ -e obj\Debug\$(TESTNAME).lst ] ; then \
rm -rf obj\Debug\$(TESTNAME).lst ; \
fi
@if [ -e bin\Debug\$(TESTNAME).ELF ] ; then \
rm -rf bin\Debug\$(TESTNAME).ELF ; \
fi
@if [ -e bin\Debug\$(TESTNAME).bin ] ; then \
rm -rf bin\Debug\$(TESTNAME).bin ; \
fi
@rm -rf *.crf
@rm -rf *.plg
@rm -rf *.tra
@rm -rf *.htm
@rm -rf *.dep
@rm -rf *.d
@rm -rf *.lnp
@rm -rf *.bak
@rm -rf *.lst
@rm -rf *.axf
@rm -rf *.sct
@rm -rf *.__i
@rm -rf *._ia
SHELL=C:\Windows\System32\cmd.exe
Čo som zatiaľ zistil počas prace s MCU.
Na ich
evaluation board schéma v prílohe, je nutne vyspajkovať R11 a na spájkovať na pozíciu R10 inak bude potrebne pri každom reprograme vypnúť zapnúť napájanie pcb
Interne hodiny je nutne kalibrovať inak periférie ako UART (dosť ma to zamestnalo až kým som nepozrel ako majú spravene wiznet funkciu
) od neskalibrovaných interných hodín nebu fungovať, nikde to v datasheete ani reference manuály nie je písané že je potrebne niečo kalibrovať našiel som to u nich na
fóre keď sa nato vypytoval jeden korejec.
Ich
v podstate okrem tej kalibrácie nič viac nerobí
takže som musel napísať svoju funkciu ktorá umožni inicializovať interne alebo externe hodiny nastaviť variabilne frekvenciu jadra a zapínať Clk deliť, pre jednotlivé periférie ktoré chcem použiť a ostatne vypnúť nakoľko defaultne je všetko zapnute
Kód: Vybrat vše
#define F_XTAL 8000000UL
#define F_INTO 8000000UL
uint32_t clk_init( const uint8_t M, const uint8_t N, const uint8_t OD, const uint8_t oscilator_select)
{
uint32_t temporary_freq = 0;
CRG->PLL_PDR = CRG_PLL_PDR_NRMLOP; // PLL power up
if (!oscilator_select) // internal oscilator set
{
//*************************************** Calibrate internal VCO calibrate value is write from factory in W7500x_INFO_BGT and W7500x_INFO_OSC *******************************
(*((volatile uint32_t *)(W7500x_TRIM_BGT))) = (*((volatile uint32_t *)(W7500x_INFO_BGT)));
(*((volatile uint32_t *)(W7500x_TRIM_OSC))) = (*((volatile uint32_t *)(W7500x_INFO_OSC)));
//*************************************** END Calibrate internal VCO ********************************************************************************************************
temporary_freq = F_INTO;
CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK; // PLL input clock internal oscilator
}
else // set external oscilator
{
temporary_freq = F_XTAL;
CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK; // PLL input clock external oscilator
}
//CRG->OSC_PDR = CRG_OSC_PDR_PD; // internal osc power down
// F_CPU = F_XTAL * M/N * 1/OD see reference manual page 44
CRG->PLL_FCR = ((uint32_t)M << 16) | ((uint32_t)N << 8) | (uint32_t) OD; // ad value in pll calculate register
CRG->PLL_OER = CRG_PLL_OER_EN; // PLL output clk enable
CRG->PLL_BPR = CRG_PLL_BPR_DIS; // PLL bypass disable if bypass enable PLL CLKIN == PLL CLKOUT;
//******************************************************* set FLCK ***********************************************
CRG->FCLK_SSR = CRG_FCLK_SSR_MCLK;// select source clock FCLK [ PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV1; // prescaler for FLCK clock
//*************************************************** End set FLCK ***********************************************
//******************************************************* set ADCCLK ***********************************************
CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_DIS;// select source clock ADCCLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV1; // prescaler for ADCCLK clock
//*************************************************** End set ADCCLK ***********************************************
//******************************************************* set SSPCLK ***********************************************
CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_DIS;// select source clock SSPCLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; // prescaler for SSPCLK clock
//*************************************************** End set SSPCLK ***********************************************
//******************************************************* set UARTCLK ***********************************************
CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_MCLK;// select source clock UARTCLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV1; // prescaler for UARTCLK clock
//*************************************************** End set UARTCLK ***********************************************
//******************************************************* set TIMER0CLK ***********************************************
CRG->TIMER0CLK_SSR = CRG_TIMERCLK_SSR_DIS;// select source clock TIMER0CLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->TIMER0CLK_PVSR = CRG_TIMERCLK_PVSR_DIV1; // prescaler for TIMER0CLK clock
//*************************************************** End set TIMER0CLK ***********************************************
//******************************************************* set TIMER1CLK ***********************************************
CRG->TIMER1CLK_SSR = CRG_TIMERCLK_SSR_DIS;// select source clock TIMER1CLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->TIMER1CLK_PVSR = CRG_TIMERCLK_PVSR_DIV1; // prescaler for TIMER1CLK clock
//*************************************************** End set TIMER1CLK ***********************************************
//******************************************************* set PWM0CLK ***********************************************
CRG->PWM0CLK_SSR = CRG_PWMCLK_SSR_DIS;// select source clock PWM0CLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->PWM0CLK_PVSR = CRG_PWMCLK_PVSR_DIV1; // prescaler for PWM0CLK clock
//*************************************************** End set PWM0CLK ***********************************************
//******************************************************* set PWM1CLK ***********************************************
CRG->PWM1CLK_SSR = CRG_PWMCLK_SSR_DIS;// select source clock PWM1CLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->PWM1CLK_PVSR = CRG_PWMCLK_PVSR_DIV1; // prescaler for PWM1CLK clock
//*************************************************** End set PWM1CLK ***********************************************
//******************************************************* set PWM2CLK ***********************************************
CRG->PWM2CLK_SSR = CRG_PWMCLK_SSR_DIS;// select source clock PWM2CLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->PWM2CLK_PVSR = CRG_PWMCLK_PVSR_DIV1; // prescaler for PWM2CLK clock
//*************************************************** End set PWM2CLK ***********************************************
//******************************************************* set PWM3CLK ***********************************************
CRG->PWM3CLK_SSR = CRG_PWMCLK_SSR_DIS;// select source clock PWM3CLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->PWM3CLK_PVSR = CRG_PWMCLK_PVSR_DIV1; // prescaler for PWM3CLK clock
//*************************************************** End set PWM3CLK ***********************************************
//******************************************************* set PWM4CLK ***********************************************
CRG->PWM4CLK_SSR = CRG_PWMCLK_SSR_DIS;// select source clock PWM4CLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->PWM4CLK_PVSR = CRG_PWMCLK_PVSR_DIV1; // prescaler for PWM4CLK clock
//*************************************************** End set PWM4CLK ***********************************************
//******************************************************* set PWM5CLK ***********************************************
CRG->PWM5CLK_SSR = CRG_PWMCLK_SSR_DIS;// select source clock PWM5CLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->PWM5CLK_PVSR = CRG_PWMCLK_PVSR_DIV1; // prescaler for PWM5CLK clock
//*************************************************** End set PWM5CLK ***********************************************
//******************************************************* set PWM6CLK ***********************************************
CRG->PWM6CLK_SSR = CRG_PWMCLK_SSR_DIS;// select source clock PWM6CLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->PWM6CLK_PVSR = CRG_PWMCLK_PVSR_DIV1; // prescaler for PWM6CLK clock
//*************************************************** End set PWM6CLK ***********************************************
//******************************************************* set PWM7CLK ***********************************************
CRG->PWM7CLK_SSR = CRG_PWMCLK_SSR_DIS;// select source clock PWM7CLK [ Disable, PLL = MCLK , INT OSC = RCLK, EXTERNAL OSC = OCLK ]
CRG->PWM7CLK_PVSR = CRG_PWMCLK_PVSR_DIV1; // prescaler for PWM7CLK clock
//*************************************************** End set PWM7CLK ***********************************************
//CRG->PLL_FCR = 0x50200; default value
// OD = (1 << (OD & 0x02)) * (1 << (OD & 0x01));
return temporary_freq * M/N * 1/(1 << (OD & 0x02)) * (1 << (OD & 0x01)); // return value of PLL frequency this value is use in peripherals for calculate
}
UART2 funguje z ich knižnice v poriadku .... takže idem sa venovať TOE nakoľko oni tam majú univerzálnu knižnicu pre W5500 W5501 W7500 .... a je to dosť neprehľadné
